Digital IP Design - Senior Lead Engineer
Core
Architecting and developing complex IPs and subsystems for automotive self-driving vehicles (ADAS), vision, radar, and in-vehicle networks.
Role type
Senior Individual Contributor Digital IP Design Lead Engineer
Builds
Complex IP blocks and subsystems for automotive SoCs
Domain
Automotive semiconductor design (ADAS, Vision, Radar)
Required skills
HDL design (Verilog/VHDL), High-speed serial protocols (PCIe, USB, MIPI CSI/DSI), Memory interfaces (DDR4, LPDDR4, QuadSPI), Microcontroller architecture (AHB/AMBA AXI), Custom processor design with DSP functions, CDC/RDC design, IP Synthesis, DFT ATPG, FPGA/Emulation validation, C/C++ for hardware modeling, Perl/Tcl scripting
Preferred skills
Automotive protocols (LIN, CAN, Flexray), Testbench/Testplan development, Pre-silicon validation
Technologies
Verilog, VHDL, Perl, Tcl, C, C++, PCIe, USB, MIPI CSI, DSI, DDR4, LPDDR4, QuadSPI, AHB, AMBA AXI, FPGA, Emulation
Responsibilities
Architect and design complex IP and subsystems across ADAS protocols; Lead IP/subsystem development from concept to implementation; Ensure quality adherence and implement process improvements; Collaborate with global systems experts on end-to-end design flow.
Seniority
Senior, hands-on IC
