Senior Lead Verification Engineer, Digital IP
Core
Pre-silicon verification of IP modules and subsystems for cost-sensitive, low-power to high-performance multi-cohort SoCs compliant with automotive and industrial safety/security standards.
Role type
Senior IC verification engineer (digital IP)
Builds
Industry-leading SoC design solutions for Automotive, IoT, Networking, and RF business lines
Domain
Semiconductor hardware engineering (SoC, Digital IP)
Deliverable
production ML models | product features
Required skills
UVM methodology, Verilog/System Verilog, C/C++, directed and constrained random methodologies, functional and code coverage, formal verification, assertion-based verification, RTL simulation, regression testing, coverage analysis
Preferred skills
Perl/TCL/Python scripting, pre- and post-silicon debugging
Technologies
UVM, RTL, FPGA, Emulation platforms
Responsibilities
Define and write IP verification plans based on requirements and architecture; Interface with HW, FW, SW, and system engineering teams; Architect, develop, debug, and run UVM-based verification environments; Create test cases, stimulus, and assertions; Run regression and analyze code/functional coverage
Seniority
Senior, hands-on IC
