Lead PDN EMIR Engineer
Core
Lead full-chip and subsystem-level Power Distribution Network (PDN) signoff, power integrity closure, and chip-package co-optimization for complex SoCs.
Role type
Senior IC physical design engineer (PDN/Power Integrity)
Builds
Production SoCs with validated power integrity and thermal performance
Domain
Semiconductor design, Physical Design, Power Integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
PDN signoff, Power Integrity analysis, IR/EM analysis, VLSI design, Chip-package co-optimization, Power grid architecture, Bump planning, Decap methodology, Thermal-aware analysis, TCL/Python/Shell scripting, EDA tool integration
Preferred skills
Next-generation PDN methodologies, Automation of PDN flows, Regression infrastructure development, Cross-functional collaboration with Physical Design/DFT/Package teams, Silicon bring-up and debug, Technical mentorship
Technologies
Ansys, Cadence, Synopsys, TCL, Python, Shell
Responsibilities
Own full-chip PDN signoff, Define PDN signoff criteria, Drive power integrity closure across modes, Lead package-aware IR/EM analysis, Develop next-generation PDN methodologies, Automate PDN flows, Collaborate with Physical Design teams on floorplanning and routing, Mentor engineers and define training content, Present signoff status to management
Seniority
Senior, hands-on IC with mentorship responsibilities
