Senior Principal Engineer
Core
Digital Design Engineer responsible for scan insertion, ATPG, and GLS to enable DFT flows during synthesis.
Role type
Senior Principal Engineer (Digital Design / DFT)
Builds
Scan insertion collaterals and DFT flows for implementation teams
Domain
Semiconductor / Digital Design / Design for Test (DFT)
Required skills
Scan insertion, ATPG, GLS, DFT architecture, fault modeling, coverage analysis, IEEE 1149.1 (JTAG), IEEE 1687 (IJTAG)
Preferred skills
Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test, partition-level ATPG, SoC-level ATPG
Technologies
Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test
Responsibilities
Understand DFT architecture of the design, provide scan insertion collaterals to the implementation team, contribute to ATPG at partition and SoC level, perform DFT GLS simulation and coverage analysis
Seniority
Senior, hands-on IC
