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Senior Analog Mixed Signal Verification Engineer

Chandler (Office)💼 Full-time🗓 2026-08-12 → 2026-09-26

Core

Lead verification for automotive and industrial PMIC products from specification through signoff, ensuring functional correctness, safety, and robustness.

Role type

Senior IC analog mixed-signal verification engineer

Builds

Production PMIC and power-conversion products for automotive and industrial markets

Domain

Semiconductor / Power Management ICs

Deliverable

production ML models | product features

Required skills

Analog and mixed-signal circuit fundamentals, Verilog-AMS, SystemVerilog, UVM, constrained-random verification, coverage-driven verification, regression automation, formal verification, low-power verification, EDA tool proficiency, scripting languages (Python, Perl, Tcl, Shell)

Preferred skills

Requirements traceability methodologies, cross-functional team leadership, mentoring junior engineers

Technologies

Cadence, Synopsys, Siemens EDA, Verilog-AMS, SystemVerilog, UVM, RNM

Responsibilities

Define verification strategies, environments, and coverage objectives; Develop and validate mixed-signal simulation environments and reusable components; Execute test planning, debug, and signoff; Bridge digital and mixed-signal verification flows; Track development metrics and drive methodology improvements

Seniority

Senior, hands-on IC with technical leadership

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