Principal Digital Verification Engineer (mfd)
Core
Own verification of submodules including verification IPs and testbenches for ASIC/SoC designs.
Role type
Principal Digital Verification Engineer
Builds
Verification IPs and testbenches for integrated subsystems
Domain
Semiconductor / ASIC / SoC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM methodology, Metric Driven Verification, directed and constrained random methodologies, formal verification, assertions, Python, C, bash/tcsh, tcl, version control systems
Preferred skills
VHDL
Technologies
System Verilog, UVM, Python, C, bash, tcl, SVN, GIT, Clearcase
Responsibilities
Define verification strategy and metrics, review design specifications, collaborate with architects and leads, document verification activities and reports, resolve issues with HW/SW designers, maintain DV process and methodology, stay updated on verification tools and techniques
Seniority
Senior, hands-on IC
