Senior Staff Engineer Digital Verification
Core
Develop SystemVerilog–UVM testbenches, debug failing test cases, and define functional coverage models for complex IPs/SoCs.
Role type
Senior Staff IC digital verification engineer
Builds
Verification testbenches and coverage models for IP/SoC designs
Domain
Semiconductor hardware verification
Required skills
SystemVerilog, UVM, C++, Python, Perl, Linux, EDA tools, functional coverage modeling, formal verification methodology
Preferred skills
ISO26262 functional safety knowledge
Technologies
SystemVerilog, UVM, C++, Python, Perl, Linux, EDA tools
Responsibilities
Develop SystemVerilog–UVM testbenches, debug failing test cases to root cause, define and write functional coverage models, participate in design reviews, contribute to verification strategy and architecture, ensure testbenches meet sign-off targets, identify sub-modules for formal verification, proactively increase verification efficiency
Seniority
Senior Staff, hands-on IC
