Senior Staff Engineer Digital Verification (f/m/div)
Core
Define verification plans and create/improve verification environments for digital or digital mixed-signal designs.
Role type
Senior Staff Engineer, Digital Verification
Builds
Digital and mixed-signal chip designs
Domain
Semiconductor / Hardware Design
Required skills
SystemVerilog, UVM, RTL verification, gate-level verification, technical leadership, mentoring, methodology development
Preferred skills
Technical leadership experience
Technologies
SystemVerilog, UVM
Responsibilities
Create and define verification plans for digital or digital mixed signal designs; Create new and improve existing verification environments in SystemVerilog/UVM; Write and execute tests for RTL and gate-level; Debug issues in design and verification environments; Lead and coordinate other verification engineers in projects; Closely cooperate with architects, designers and other verification engineers; Mentoring of junior colleagues, consultants and students; Contribute to enhancement of existing methodologies and flows
