Staff Engineer Verification -IP Digital Functional Verification
Core
Lead subtasks in IP/SoC verification and contribute significantly to the verification of complex IPs/SoCs.
Role type
Staff Engineer, IP Digital Functional Verification
Builds
Verification environments and testbenches for complex semiconductor IPs and SoCs
Domain
Semiconductor / VLSI Design
Required skills
ASIC verification methodologies, SystemVerilog, UVM, RTL simulation, formal verification, gate-level simulation, IP/SoC testbench development
Preferred skills
Power-aware verification, verification infrastructure development
Technologies
Verilog, SystemVerilog, UVM, RTL, Formal Verification, Gate-level Simulation
Responsibilities
Lead subtasks in IP/SoC verification, Create verification requirements at the IP/SoC level, Support the development of verification infrastructure, Support different areas of IP verification including RTL simulation, formal verification, power-aware verification, and gate-level simulation
