Lead I/O Design Engineer
Core
Design and validate high-performance I/O circuits for advanced semiconductor SoCs, including GPIO, LVDS, DDR, and SerDes support.
Role type
Lead I/O Circuit Design Engineer
Builds
Production-ready IO IP solutions for semiconductor SoCs
Domain
Semiconductor / Analog Mixed-Signal Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Transistor-level design, Signal integrity analysis, ESD protection design, Layout review, Silicon bring-up, Cadence Virtuoso, SPICE simulation, CMOS device physics, IO architectures, Analog circuit design
Preferred skills
DDR4/DDR5/LPDDR interface design, Package modeling, IBIS model generation, Python/Perl/Tcl/SKILL scripting, Silicon validation
Technologies
Cadence Virtuoso, Spectre, HSPICE, FineSim, IBIS, IBIS-AMI
Responsibilities
Design custom IO circuits (GPIO, LVDS, DDR, SerDes), Perform transistor-level design and simulation, Conduct pre/post-layout simulations, Perform signal integrity analysis, Drive layout reviews, Support silicon bring-up and characterization
Seniority
Senior, hands-on IC