Senior SOC Design For Test Engineer
Core
Define, implement, verify, and support advanced Design for Test (DFT) solutions for complex SoC products in leading-edge semiconductor technologies for Automotive and Industrial applications.
Role type
Senior IC DFT Engineer
Builds
DFT architectures and manufacturing test solutions for SoC products (via careerplan.io/jobs/R-10065736-senior-soc-design-for-test-engineer-at-nxp)
Domain
Semiconductor / Digital Design / Test Engineering
Required skills
DFT methodologies (Scan, ATPG, Memory BIST, Logic BIST, JTAG), Digital design fundamentals, ASIC/SoC development flows, Verilog/SystemVerilog, DFT tools (Synopsys TestMAX, Cadence Modus, Siemens Tessent), AI-driven scripting (TCL, Python, Perl)
Preferred skills
Silicon bring-up and post-silicon debug, ATE test development, Advanced semiconductor process technologies, Automotive/Industrial product experience
Technologies
Synopsys TestMAX, Cadence Modus, Siemens Tessent, Verilog, SystemVerilog, TCL, Python, Perl
Responsibilities
Define and implement DFT architectures at IP, subsystem, and SoC levels; Develop and integrate DFT features including Scan, ATPG, and BIST; Execute ATPG patterns to achieve target fault coverage; Perform DFT verification, simulations, and validation; Collaborate with design, verification, and physical design teams; Support silicon bring-up and post-silicon evaluation; Analyze test results and debug failures to drive yield improvements; Work with manufacturing and ATE teams to enable production test flows; Evaluate and adopt new DFT methodologies and tools; Document DFT architecture and test plans; Provide technical leadership and mentorship to junior engineers.
Seniority
Senior, hands-on IC
