Stage Ingénieur : Conception Numérique SoC - Design for Test (F/H)
Core
Intern role focused on Design-for-Test (DFT) for complex System-on-Chip (SoC) development in secure transaction applications.
Role type
Digital SoC Design-for-Test Intern
Builds
Test sequences and DFT methodologies for mixed-signal integrated circuits
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design (VHDL/Verilog), digital logic fundamentals, DFT concepts, scripting (Python/Perl/Tcl)
Preferred skills
exposure to production testing
Technologies
VHDL, Verilog, Python, Perl, Tcl
Responsibilities
Understand DFT architecture in SoCs, develop test sequences for fault coverage, simulate and debug test sequences, evaluate DFT methodologies, collaborate with design and verification teams, document and present results
Seniority
Intern
