Stage Ingénieur : Conception Numérique SoC - Design for Test (F/H)
Core
Design-for-Test (DFT) intern developing test sequences and methodologies for complex System-on-Chip (SoC) designs.
Role type
Intern, Digital SoC Design Engineer (DFT)
Builds
Test sequences and DFT methodologies for mixed-signal integrated circuits
Domain
Semiconductor / Digital IC Design
Required skills
RTL design (VHDL/Verilog), Digital logic fundamentals, DFT concepts, Scripting (Python/Perl/Tcl), Simulation and debugging
Preferred skills
Production test exposure, Flow improvement analysis
Technologies
VHDL, Verilog, Python, Perl, Tcl, CAD environments
Responsibilities
Develop test sequences to optimize fault coverage, Perform simulation and debugging of test sequences, Evaluate DFT methodologies, Collaborate with design and verification teams, Document and present results
Seniority
Intern
