Stage Ingénieur : Techniques de vérification basse consommation utilisant l'UVM, les preuves formelles et les capacités de l'IA (H/F)
Core
Intern engineer role focused on improving digital verification of Power Management in NFC components using UVM, formal proofs, and AI exploration.
Role type
Intern, Digital Verification Engineer (Power Management)
Builds
NFC components for secure mobile transactions, payments, and IoT
Domain
Semiconductor / Integrated Circuits / Power Management
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Formal Verification (Jasper), Analog/Mixed-Signal concepts, SoC architecture analysis, Testbench development, Coverage analysis
Preferred skills
AI/ML for verification, IP verification, SoC verification
Technologies
SystemVerilog, UVM, Jasper, wreal models
Responsibilities
Analyze SoC power-management architecture (power gating, reset, clocking); Develop and execute SystemVerilog test scenarios; Implement SVA assertions; Use Jasper for formal verification of power controllers; Investigate AI/ML tools for analog/mixed-signal verification
Seniority
Intern, final year engineering student
