Lead DFT Engineer
Core
Design and implement Digital Test (DFT) architectures, including scan insertion and ATPG, to enable testability in semiconductor designs.
Role type
Lead DFT Engineer
Builds
Testable semiconductor chips and SoCs
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan insertion, ATPG, GLS, DFT architecture design, fault modeling, coverage analysis, IEEE 1149.1 (JTAG), IEEE 1687 (IJTAG), Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test
Preferred skills
SoC level ATPG contribution, DFT GLS simulation methodologies
Technologies
Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test
Responsibilities
Understand DFT architecture of the design, provide scan insertion collaterals to the implementation team, contribute to ATPG at partition and SoC level, perform DFT GLS simulation and coverage analysis
Seniority
Senior, hands-on IC
