<Data center>Design Engineer - Die-to-Die Interface
Core
Design and implement Die-to-Die (D2D) and UCIe digital IP blocks for high-bandwidth, low-latency communication across chiplets in HPC SoCs.
Role type
IC digital design engineer (chiplet interconnects)
Builds
Digital IP blocks for chiplet interconnects
Domain
Semiconductor / High-Performance Computing
Required skills
Digital IP design, UCIe protocol knowledge, D2D interface design, Timing closure, Design-for-Test (DFT), Verification planning, Cross-functional collaboration
Preferred skills
Advanced Packaging technologies, Mixed-mode design, Firmware co-design
Technologies
UCIe, D2D, HPC SoC
Responsibilities
Develop Die-to-die and UCIe digital IP for HPC SoC; Integrate D2D controller and PHY to timing closure and DFT; Define interface specifications and create verification plans; Collaborate with mixed-mode designers and firmware engineers.
Seniority
Individual Contributor (IC), open to recent graduates or experienced architects
