<Data Center> HBM IP Subsystem End-to-End Solution Leader
Core
Own end-to-end technical quality of the HBM memory subsystem (Memory Controller, PHY, and HBM KGSD) for data center AI silicon from RTL freeze through high-volume production.
Role type
Senior IC solution leader (HBM IP subsystem)
Builds
Data center AI silicon with HBM memory subsystem
Domain
Semiconductor / AI / High Bandwidth Memory
Deliverable
production ML models
Required skills
HBM memory subsystem architecture, Memory Controller design, PHY design, HBM KGSD, RTL design, pre-silicon quality analysis, post-silicon test quality, cross-functional technical leadership
Preferred skills
RTL freeze management, high-volume production readiness, DRAM supplier collaboration, OSAT collaboration
Technologies
HBM, Memory Controller, PHY, KGSD, RTL
Responsibilities
Define quality gates for HBM MC, PHY, and HBM KGSD; arbitrate technical evidence; close the loop between pre-silicon predictions and post-silicon reality; manage pre-silicon quality checks; manage post-silicon production readiness checks
Seniority
Senior, hands-on IC
