<Data center>TOP Designer & FE Integrator
Core
Designing top-level integrated circuits for testing, including uArch, DFT, and PAD top, and integrating front-end sensors and IOs for simulation and post-Si validation.
Role type
Senior IC Design Engineer (Test & Integration)
Builds
Integrated circuit topologies, sensor integration blocks, and test sequences for silicon validation.
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
uArch design, DFT top design, PAD top design, eFUSE integration, PVT sensor integration, aging sensor integration, IO integration, test sequence preparation, RFI/RFQ management
Preferred skills
Simulation expertise, customer requirement synchronization
Technologies
uArch, DFT, PAD, eFUSE, PVT sensors, aging sensors
Responsibilities
Design DFT and PAD top structures for testing; Integrate front-end sensors and IOs based on customer requirements; Prepare test sequences for Post-Si test and HTOL; Manage RFI/RFQ processes to sync customer testing structures and requirements.
