Physical Verification Sign-off Engineer
Core
Full-chip Physical Verification Sign-off for tape-out, covering DRC, LVS, ANT, ERC, ESD, and PERC.
Role type
Physical Verification Engineer
Builds
Tape-out ready chip layouts
Domain
Semiconductor / Physical Design
Required skills
DRC, LVS, ANT, ERC, ESD, PERC, full-chip layout integration, IP coordination, manufacturing coordination, automation scripting
Responsibilities
Perform full-chip physical verification sign-off; Resolve full-chip layout integration issues with Place & Route team; Coordinate with internal IP owners on IP-related issues; Coordinate with Manufacturing Team on DRC issues; Provide automation solutions to improve tape-out flow efficiency; Report on tape-out issues
