[2027 Campus Hire] IC Physical Design Engineer
Core
IC physical design of 12nm/6nm/4nm and below advanced process chips, handling RTL to GDS flow including synthesis, APR, and signoff.
Role type
IC physical design engineer
Builds
Advanced process chips (12nm/6nm/4nm and below)
Domain
Semiconductor / IC Physical Design
Required skills
RTL to GDS flow, Synthesis, APR (auto place and route), Signoff, Block ownership, Floorplanning, Partitioning, Hierarchical chip design
Preferred skills
Block coordination, Critical issue resolution, Tape out responsibility
Technologies
12nm, 6nm, 4nm processes
Responsibilities
Perform block-level physical design for 2-3 million instances, coordinate 5-10 blocks to solve critical issues, manage floorplan and partition for hierarchical chips with 20+ million instances and 500+ macros, execute full chip tape out.
Seniority
Campus Hire (Entry Level)
