[2027 Campus Hire] Design Verification Engineer
Core
Design verification for modules, IPs, and System-on-Chip (SoC) using coverage-driven methodologies.
Role type
Design Verification Engineer
Builds
Verification environments, testbenches, and verification IP for semiconductor designs.
Domain
Semiconductor / Hardware Design
Required skills
UVM, SystemVerilog, Verilog, SystemC, Randomization-based verification, Coverage closure, Formal verification, Low Power verification, Verification automation
Preferred skills
Module/IP/SOC design experience, Test plan development
Technologies
UVM, SystemVerilog, Verilog, SystemC
Responsibilities
Develop and review test plans; Develop verification environment/testbench; Implement test with randomization-based coverage driven verification; Implement functional and functional/code coverage closure; Hands-on code/debug; Low Power verification; Formal verification; Verification automation flow
