Senior/Staff Layout engineer
Core
Full-custom layout for analog and mixed-signal IPs (ADCs, PLLs, LDOs, bandgaps, high-speed interfaces) for next-generation wireline and optical transceivers in data centers and AI/HPC.
Role type
Senior/Staff IC layout engineer (analog/mixed-signal)
Builds
Analog and mixed-signal IPs for wireline and optical transceivers
Domain
Semiconductor design, analog/mixed-signal, data center, AI, high-performance computing
Required skills
full-custom layout, transistor-level layout, floor planning, DRC/LVS/ERC verification, post-layout simulation, EM/IR analysis, parasitic extraction
Responsibilities
Own full-custom layout for analog and mixed-signal IPs; Work closely with circuit designers to optimize layout for performance and area; Perform detailed floor planning and transistor-level layout; Ensure designs are DRC/LVS/ERC clean and meet all physical verification requirements; Support post-layout simulations and sign-off procedures; Handle LDE, EM/IR, and parasitic effects in advanced process nodes
Seniority
Senior/Staff, hands-on IC
