Senior DRAM RTL design engineer
Core
Design digital IP blocks for memory and storage solutions, managing RTL creation, integration, and full-chip verification.
Role type
Senior IC RTL design engineer (memory/DRAM)
Builds
Digital IP blocks, memory controllers, and full-chip memory designs
Domain
Semiconductor, Memory (DRAM/NAND), Digital Logic Design
Deliverable
production ML models | product features
Required skills
RTL design, asynchronous/synchronous design, CDC methodologies, SoC design flows, CMOS circuit fundamentals, memory operation principles, full-chip integration, verification (functional/timing/power/reliability), floor-planning, placement, routing
Preferred skills
DRAM design (DDR5, LPDDR5, HBM), AI/ML-assisted design flows, Spyglass tool experience, NAND memory design, SoC/ASIC semicustom flow
Technologies
Spyglass, industry standard simulators, Micron-specific simulators
Responsibilities
Design digital IP blocks from microarchitecture to RTL; define module interfaces and system-level architecture; drive full-chip integration including CDC, Lint, synthesis, STA, and power analysis; oversee layout process (floor-planning, placement, routing); perform block-level and full-chip verification; provide technical mentorship and participate in design reviews
Seniority
Senior, hands-on IC
