Senior Staff Digital Design Engineer
Core
Develop RTL designs for digital IP blocks and subsystems, translating architectural specs into synthesizable code for data center and AI infrastructure.
Role type
Senior Staff IC digital design engineer
Builds
Digital IP blocks and subsystems for connectivity, data center, and AI infrastructure
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features
Required skills
Verilog, SystemVerilog, RTL design, CDC analysis, low-power design, timing closure, synthesis, silicon bring-up, root cause analysis, mentoring
Preferred skills
DSP algorithms, UVM verification
Technologies
Verilog, SystemVerilog, UVM
Responsibilities
Develop RTL designs for digital IP blocks; Translate architectural specifications into clean, synthesizable RTL; Perform linting, CDC, and low-power design checks; Analyze timing, area, and power tradeoffs; Debug functional issues during simulation, emulation, FPGA prototyping, or silicon bring-up; Mentor new and less experienced team members
Seniority
Senior Staff, hands-on IC with mentorship
