Engineer, DEG Layout
Core
Design and develop analog, mixed-signal, custom digital block, standard cells, and full chip layouts for memory and storage solutions.
Role type
Senior IC physical design engineer (analog/mixed-signal/digital)
Builds
Custom digital blocks, standard cells, and full chip layouts for DRAM, NAND, and NOR memory products
Domain
Semiconductor manufacturing (memory and storage)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
analog layout design, mixed-signal layout design, custom digital block layout, standard cell design, full chip level layout, LVS verification, DRC verification, Antenna check, Shield check, Matching check, Latch up check, EM IR Totem checks, quality check, documentation, auto placement, route tools, skill coding, automation, project planning, area/time estimation, scheduling, delegation, execution, team leadership, sub block-level layout review, AI tools for layout effort reduction
Responsibilities
Perform layout verification including LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check, and documentation; Develop digital block layouts using auto placement and route tools; Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules; Support developing team members in executing sub block-level layouts and review their work; Contribute to effective project management; Communicate effectively with global engineering teams; Reduce layout effort using AI tools
Seniority
Senior, hands-on IC