Advanced Technology Japan Engineer, WoW Bonding
Core
Developing and optimizing wafer bonding processes for next-generation semiconductor packaging technologies.
Role type
Senior IC process engineer (wafer bonding)
Builds
High-performance memory and storage products (DRAM, NAND, NOR)
Domain
Semiconductor manufacturing / Wafer bonding
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Wafer bonding, Si grinding, Bevel trimming, DOE, SPC, FMEA, English technical communication
Preferred skills
CMP, 3D integration, LabVIEW, FPGA control, Python, MATLAB, Project leadership
Technologies
Wafer bonding equipment, Si grinding tools, Bevel trimming systems
Responsibilities
Develop and optimize wafer bonding processes; Integrate wafer bonding, Si grinding, and bevel trimming; Evaluate and upgrade equipment; Implement SPC metrics and perform abnormality analysis; Reduce risks using FMEA and 8D methodologies; Coordinate with material suppliers for quality and cost management
Seniority
Senior, hands-on IC
