Sr Manager Design Development Technical Leadership, HBM
Core
Single-threaded technical program owner for Heterogeneous Integration Group (HIG) managing end-to-end execution of High Bandwidth Memory (HBM) design achievements across DRAM, base die, test vehicles, interposers, and IP.
Role type
Senior Manager, Design Development Technical Leadership
Builds
Heterogeneous Integration (Heterogeneous Integration Group) products
Domain
Semiconductor / Memory and Storage / Heterogeneous Integration
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cross-functional program leadership, Change Control Board (CCB) process ownership, Design risk register management, Foundry and IP vendor engagement, Financial accountability for design portfolios, Roadmap integration and communication, Die size and DFM optimization, Executive stakeholder management
Preferred skills
10+ years industry experience, Formal program/project management methodologies, Knowledge of DRAM operation and HBM product family, Understanding of custom and digital design flows, Bachelor's degree in Electrical Engineering
Technologies
Jira, TSMC nodes, UMC nodes, JEDEC standards
Responsibilities
Own end-to-end execution of on-schedule delivery of HBM design achievements; Lead cross-functional dependencies across DRAM, base die, test chips, and interposers; Manage formal Change Control Board (CCB) processes and design risk registers; Lead engagement with external foundries and IP providers; Own design-phase financial accountability and mask cost planning; Serve as central owner of the HBM design roadmap; Capture customer requirements and align design execution with market priorities.
Seniority
Senior, hands-on IC