Design Methodology – Principal DRAM Power Integrity Engineer
Core
Develop and standardize EMIR methodology and perform static/dynamic EM/IR and PDN analysis for advanced DRAM products.
Role type
Principal DRAM Power Integrity Engineer
Builds
High-performance DRAM memory and storage products
Domain
Semiconductor / Memory / Power Integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
EMIR analysis, PDN analysis, Ansys RedHawk, Ansys Totem, vectorless IR-drop analysis, root-cause analysis, SoC-level signoff, end-to-end design flow understanding, automation frameworks
Preferred skills
Power-modeling, Python scripting, Tcl scripting, PnR tools, STA tools, SPICE, AI/ML-assisted design flows
Technologies
Ansys RedHawk, Ansys Totem, FusionCompiler, PrimeTime, Make
Responsibilities
Develop and standardize EMIR methodology across DRAM products; Perform static and dynamic EM/IR and PDN analysis; Leverage AI-based tools and automation for PDN analysis; Maintain understanding of full EMIR flow from netlist to silicon correlation; Partner with design and implementation teams to develop worst-case vectors; Collaborate with cross-functional teams and EDA vendors to improve methodologies; Develop dashboards to track EMIR results and support signoff.
Seniority
Senior, hands-on IC
