Principal Engineer - IP Design Verification
Core
Lead end-to-end verification strategy and architecture for complex DRAM analog and mixed-signal IPs, ensuring coverage closure and design quality for high-speed memory technologies.
Role type
Principal Engineer - IP Design Verification (Analog/Mixed-Signal)
Builds
Production-ready memory IP blocks (DDR5, LPDDR5, DDR6, LPDDR6) operating at speeds up to 9600MT/s
Domain
Semiconductor / Memory / Analog & Mixed-Signal Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog and Mixed-signal verification, Block-level Analog/Digital verification coverage, PowerUp verification, Reliability/ESIRA simulations, Behavioral model development, Functional and timing checks coverage, Chip-level verification, Multi-IP integration, High-bandwidth architectures, Spice/Mixed signal/Digital simulations, Verilog Models, Verilog A/MS, RVM model writing, Debugging, AI-based automation for verification
Preferred skills
Mentoring/Training/Leading Analog/Mixed blocks verification, Experience with Virtuoso, Primesim/Finseim, Hspice, Xcellium, Simvision, Waveview, Verdi/Verisium, AI-assisted tools for verification productivity
Technologies
Virtuoso, Primesim, Finseim, Hspice, Xcellium, Simvision, Waveview, Verdi, Verisium, Verilog, Verilog A, RVM
Responsibilities
Guide and set the direction for the verification effort within areas of expertise, Own end-to-end verification strategy for DRAM analog and mixed-signal IPs, Define and review verification plans ensuring completeness and risk mitigation, Drive block-level, top-level, and full-chip analog verification sign-off, Own verification architecture, test planning, and sign-off for complex IPs or chip-level designs, Define functional, code, and assertion coverage strategy and drive coverage closure, Identify verification risks early and architecture decisions to improve design quality
Seniority
Principal, hands-on IC with mentorship
