SMTS Design Verification Engineer
Core
Own pre-silicon functional verification for a high-speed interface chip program, building environments to give confidence in RTL before silicon commitment.
Role type
Senior IC Design Verification Engineer (High-Speed Interface/PHY)
Builds
Pre-silicon verification environments for custom analog PHYs and soft IP functions (Error Counting, Eye Monitor, I2C management)
Domain
Semiconductor / Memory and Storage / High-Speed Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM/SystemVerilog environment expertise, building testbench environments from scratch, serial management interface verification (I2C, SPI, APB, AHB), coverage-driven verification methodology, debugging simulation waveforms and RTL, formal property checking
Preferred skills
Formal property verification (JasperGold, VC Formal), PHY functional modeling/behavioral simulation, real-number modeling (RNM) or Verilog-AMS, PRBS pattern generation and error detection verification, post-silicon validation and ATE test vector development
Technologies
UVM, SystemVerilog, JasperGold, VC Formal, Verilog-AMS, PRBS
Responsibilities
Develop and maintain full-chip DV plan and coverage targets; Build and maintain UVM/SystemVerilog verification environments for key design blocks; Write directed and constrained-random tests to achieve functional and code coverage closure; Implement SystemVerilog Assertions (SVA) for critical control sequences; Apply formal property checking for CSR correctness and CDC properties; Build and maintain regression infrastructure and triage failures; Provide debug waveforms and test vectors for post-silicon bring-up and ATE development
Seniority
Senior, hands-on IC
