Mixed-Signal Design Verification Engineer | Custom
Core
Executing pre-silicon verification of complex mixed-signal IC products, specifically high-speed wireline communications and clock/data paths, by building scalable automated testbenches and behavioral models.
Role type
Senior Mixed-Signal Design Verification Engineer (Custom ICs)
Builds
Automated AMS and DMS testbenches for custom high-volume chips
Domain
Semiconductor IC design, high-speed wireline communications, clock/data recovery
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mixed-signal and digital verification flows (AMS/DMS/TLDV/DDV), analog block modeling, schematic-level analog design understanding, RTL/digital design knowledge, timing verification across analog/digital boundaries, automation tool/scripting development, debug skills
Preferred skills
USB protocol verification (USB2.0, eUSB), analog block modeling with SystemVerilog EEnet, SerDes/re-timer verification, Verification IP (VIP) development
Technologies
Verilog, SystemVerilog, Verilog-AMS, Cadence Virtuoso, Spectre, Simvision, Starfish, CDDS
Responsibilities
Build scalable testbench and automation solutions for DMS and AMS stimulus; Verify high-speed clock and data paths (PLLs, DLLs, SerDes); Collaborate with design teams on verification architecture and bug triage; Create and maintain behavioral models of analog circuits; Evaluate and simulate system-level use cases
Seniority
Senior, hands-on IC