Engineer, DEG Mobile DRAM Verification
Core
Senior Verification Engineer responsible for end-to-end analysis and verification of sophisticated full-chip gate-level custom designs for DDR5, LPDDR5, DDR6, and LPDDR6 memory architectures operating at speeds up to 9600MT/s.
Role type
Senior IC verification engineer (memory/DRAM)
Builds
High-performance DRAM and emerging memory products for data centers, AI, 5G, and mobile applications
Domain
Semiconductor industry, memory and storage solutions, digital logic design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM Test Bench, gate-level simulation with delays, logic schematic analysis, CMOS circuit design analysis, timing analysis (setup/hold/critical path), AI-assisted verification tools
Preferred skills
Experience with PLI coding, multi-functional task execution, cross-functional collaboration on verification flows
Technologies
Verilog, SystemVerilog, UVM, simulation tools, AI-assisted verification tools
Responsibilities
Guide and set direction for verification efforts; simulate, analyze, and debug pre-silicon full-chip designs; develop test cases and stimulus to increase functional coverage; participate in developing verification methodology and environments; co-work on developing new verification flows; develop and maintain test benches and test vectors; identify verification pain points suitable for AI-based automation
Seniority
Senior, hands-on IC
