NCG Pathfinding Design Layout Engineer
Core
Design and development of critical analog, mixed-signal, custom digital blocks and full chip level integration support for memory and storage solutions.
Role type
Analog/Mixed-Signal Layout Design Engineer
Builds
Custom digital blocks and full chip layouts for DRAM, NAND, and NOR memory products
Domain
Semiconductor manufacturing / Memory and storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout fundamentals (matching, electro-migration, latch-up, coupling, crosstalk, IR-drop), design constraint implementation, LVS/DRC/Antenna verification, block-level layout delivery
Preferred skills
Physical verification of custom layout, Cadence VLE/VXL, Mentor Graphic Calibre DRC/LVS, layout impact analysis (speed, capacitance, power, area)
Technologies
Cadence VLE/VXL, Mentor Graphic Calibre
Responsibilities
Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support; Perform layout verification like LVS/DRC/Antenna, quality check and documentation; Responsible for on-time delivery of block-level layouts with acceptable quality; Effectively communicating with Global engineering teams to assure the success of layout project
Seniority
Entry-level (0-2 years experience)
