Principal Digital Designer, HIG HBM
Core
Lead front-end digital design and RTL architecture for next-generation High Bandwidth Memory (HBM) products.
Role type
Principal IC RTL Designer (Memory/Storage)
Builds
High Bandwidth Memory (HBM) subsystems and silicon
Domain
Semiconductor, Memory, ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL architecture, micro-architecture, timing closure, power optimization, area trade-offs, synthesis, static timing analysis (STA), constraint management, formal verification (LEC), linting, clock domain crossing (CDC), sign-off methodologies
Preferred skills
UPF, power-intent development, DFT/scan insertion, ATPG, timing model generation, Python/Perl scripting, place-and-route tools
Technologies
RTL, Synthesis, STA, LEC, Lint, CDC, UPF, Python, Perl
Responsibilities
Define and architect advanced RTL blocks for HBM subsystems; Own end-to-end front-end design including micro-architecture and simulation strategy; Drive technical decisions across circuit development and physical-design integration; Champion design methodologies and reusable frameworks; Collaborate with physical design, verification, and architecture teams; Lead root-cause analysis for complex design issues
Seniority
Principal, hands-on IC with technical leadership
