Member Of Technical Staff TLP - HBM Verification
Core
Drive verification architecture and methodology for next-generation HBM designs, ensuring robust sign-off strategies and developing novel solutions for verification workflows.
Role type
Senior IC silicon verification engineer (HBM)
Builds
Next-generation HBM memory chips
Domain
Semiconductor / Memory / HBM
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Formal Verification, SoC architecture, bus protocols (AXI, PCIe), low-power design, simulation, coverage analysis, regression management, team leadership
Preferred skills
AMS Co-Simulation, mixed-signal verification, Python/TCL scripting, AI tools (Copilot/Claude)
Technologies
UVM, Formal Verification tools, EDA tools, SystemVerilog
Responsibilities
Define and drive verification architecture and methodology for next generation HBM designs; Develop verification plans, coverage strategies, and sign-off criteria; Architect and implement UVM-based testbenches and reusable verification components; Apply Formal Verification techniques for critical paths; Collaborate with build teams to ensure verification completeness and quality; Mentor and guide verification engineers on guidelines and advanced methodologies; Evaluate and integrate AMS Co-Simulation techniques for mixed-signal IP verification; Work closely with EDA vendors to adopt the latest tools and flows.
Seniority
Senior, hands-on IC
