Member Of Technical Staff TLP - HBM Verification
Core
Drive verification architecture and methodology for next-generation HBM designs, ensuring robust sign-off strategies and developing novel solutions for verification workflows.
Role type
Senior IC silicon verification engineer (HBM)
Builds
Next-generation HBM memory chips
Domain
Semiconductor / Memory / HBM
Required skills
SystemVerilog, UVM, Formal Verification, SoC architecture, bus protocols (AXI, PCIe), low-power design, simulation, coverage analysis, regression management, AMS Co-Simulation, AI tools (Copilot/Claude)
Preferred skills
DDR/GDDR/LPDDR memory verification, SerDes PHY IP verification, Python/TCL scripting, EDA vendor tools
Technologies
UVM, SystemVerilog, Formal Verification tools, EDA tools, AI tools (Copilot/Claude)
Responsibilities
Define and drive verification architecture and methodology; Develop verification plans, coverage strategies, and sign-off criteria; Architect and implement UVM-based testbenches; Apply Formal Verification techniques; Mentor verification engineers; Evaluate and integrate AMS Co-Simulation techniques; Collaborate with build teams and EDA vendors
Seniority
Senior, hands-on IC
