SCG ArchDesign Engineer - New College Grad 2027
Core
Design and execute silicon co-design prototypes and experiments to validate power, performance, noise, and binning behavior for chips, translating results into data pipelines for architecture and manufacturing.
Role type
Senior IC silicon co-design engineer (prototyping & DOE)
Builds
Silicon prototypes, measurement setups, and data pipelines for firmware tuning and product specs
Domain
Semiconductor / GPU / Datacenter
Deliverable
production ML models
Required skills
Python, Design of Experiments (DOE), silicon characterization, power/performance analysis, data pipeline development, Git, SQL
Preferred skills
GPU/SoC/CPU experience, LLMs in engineering workflows, firmware/BIOS parameters, ATE/SLT screening
Technologies
Python, Git, SQL, LLMs
Responsibilities
Stand up silicon co-design prototypes and measurement setups; Plan and execute design of experiments (DOE) for power, performance, and binning; Build Python pipelines to analyze characterization data; Partner with architecture and firmware to iterate prototypes; Use AI-assisted workflows for experiment planning and documentation
