ASIC Subsystem Engineer (Mid-level or Lead)
Core
Define, develop, and validate next-generation multi-ASIC architectures incorporating digital signal-processing cores for digital communication subsystems supporting commercial, civil, and national security programs.
Role type
Mid-level or Lead ASIC Subsystem Engineer
Builds
Advanced ASICs and mixed-signal components for space-based digital communication systems
Domain
Aerospace / Defense / Mixed-Signal ASIC Design
Deliverable
production ML models | product features
Required skills
ASIC architecture, mixed-signal ADC/DAC design, digital signal processing, requirements allocation, verification planning, trade studies, hardware/software integration, supplier coordination
Preferred skills
VLSI design, SerDes IP procurement, built-in self-test (BIST), high-speed interface standards, system-level modeling, technical leadership
Technologies
C, MATLAB, Python, JESD, SPI, I2C, JTAG, SerDes, ADC, DAC
Responsibilities
Define and validate ADC/DAC performance requirements (ENOB, SNR, SINAD, SFDR, THD, jitter, linearity), develop design validation test plans, lead technical trade studies, coordinate ASIC design reviews and qualification activities, prepare technical reports and interface documentation
Seniority
Mid-level (5+ years) or Lead (9+ years), hands-on IC with significant technical coordination
