Physical Design and Timing Engineer Intern - Summer 2027
Core
Drive physical design, power, and timing closure for high-frequency and low-power designs, supporting the transition from RTL to GDSII.
Role type
Physical Design and Timing Engineer Intern
Builds
High-frequency, low-power integrated circuit designs
Domain
Semiconductor / Hardware Design / EDA
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), power analysis, power reduction, logic synthesis, equivalence checking, physical optimization (placement, routing, clock tree), EDA tool usage, scripting (Perl, Tcl, Make, Python), AI/ML application to design workflows
Preferred skills
Hands-on experience applying AI/ML models or LLM-based tools to EDA or physical design problems, previous work experience in physical design, methodology and flow development/automation
Technologies
Cadence, Synopsys, Siemens
Responsibilities
Run physical design experiments and help develop flows and methodologies
Seniority
Intern
