ASIC Design and Verification Intern, SOC - 2027
Core
Design and verification of complex reset/fuse/ism/sysctrl/boot and clock-related logic for latest NVIDIA products.
Role type
ASIC Design and Verification Intern
Builds
SysASIC and clock-related IPs for NVIDIA SOC products
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features
Required skills
RTL design, Verilog, SystemVerilog, simulation, synthesis, STA, lint, CDC/RDC, clock gating, clock-domain crossing, reset synchronization, PLLs, formal verification, property specification, assertion-based verification, equivalence checking, Python, Perl, Tcl, shell scripting, C, C++, Linux, EDA tools
Preferred skills
UVM, SVA, functional coverage, formal property verification, automation tools, AI-assisted methods, FPGA development, low-power design
Technologies
Verilog, SystemVerilog, UVM, SVA, Python, Perl, Tcl, C, C++, Linux, EDA tools
Responsibilities
Develop and debug Verilog/SystemVerilog RTL, testbenches, assertions, and simulation regressions; Analyze and resolve issues from simulation, formal verification, lint, CDC/RDC, synthesis, STA, and gate-level verification; Develop scripts, automation tools and AI agents to improve design and verification flows
Seniority
Intern
