ASIC Verification/Design Engineering Intern
Hybrid
Core
Intern working on next-generation ASIC development for networking chips, contributing to RTL/Physical Design and verification activities.
Role type
Intern, ASIC Verification/Design Engineering
Builds
Networking chips (ASICs) for the marketplace
Domain
Semiconductor / Networking Hardware
Required skills
Verilog, Python, C/C++, scripting (Perl/TCL), hardware design, AI tools
Preferred skills
Strong interest in high-tech, problem-solving, time management
Technologies
Verilog, Python, C, C++, Perl, TCL
Responsibilities
RTL/Physical Design, Pre-Silicon verification, post-silicon verification, Formal Verification, Script &/or Tool development, document generation
Seniority
Intern
