ASIC Design and Verification Intern, SOC - 2027
Core
Design and verification of complex reset/fuse/ism/sysctrl/boot and clock-related logic for latest NVIDIA products.
Role type
ASIC Design and Verification Intern
Builds
SysASIC and clock-related IPs for NVIDIA SOC products
Domain
Semiconductor / ASIC Design
Required skills
Verilog, SystemVerilog, RTL design, simulation, synthesis, STA, lint, CDC/RDC, clock gating, clock-domain crossing, reset synchronization, PLLs, timing fundamentals
Preferred skills
UVM, SVA, functional coverage, formal verification, Python, Perl, Tcl, shell scripting, C, C++, Linux, EDA tools
Technologies
Verilog, SystemVerilog, UVM, SVA, Python, Perl, Tcl, Linux, EDA tools
Responsibilities
Develop and debug Verilog/SystemVerilog RTL, testbenches, assertions, and simulation regressions; Analyze and resolve issues from simulation, formal verification, lint, CDC/RDC, synthesis, STA, and gate-level verification; Develop scripts, automation tools and AI agents to improve design and verification flows
Seniority
Intern
