ASIC Design Engineer (RDSS Intern)
Core
Develop multimedia IP for GPU and SOC chips as part of the RDSS (Research and Development Substitute Services) program.
Role type
ASIC Design Engineer (Intern)
Builds
Multimedia IP for GPU and SOC chips
Domain
Semiconductor / Hardware Design
Deliverable
production ML models
Required skills
Verilog, System Verilog, AI Agent workflows, AI-enabled automation, C++/SystemC modeling, Python scripting, Perl scripting, Tcl scripting, Make, shell scripting
Preferred skills
Digital build course completion, IC build implementation project experience
Responsibilities
IP level front-end design, collaborate with design verification engineers, analyze build trade-offs and optimize builds based on features and system limitations, complete task lists and deliverables
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