Staff Design Engineer
Core
Designing Debug Subsystems and SoCs using CoreSight IPs for various application segments.
Role type
Staff SoC Design Engineer
Builds
SoCs and Debug Subsystems
Domain
Semiconductor / SoC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, Verilog, ARM CoreSight IP, low-power design, clock domain crossing, reset domain crossing, Perl/Python scripting, micro-architecture specification, RTL implementation
Preferred skills
UPF/CPF, DFT concepts, physical design collaboration, floor-planning, mentoring
Technologies
Arm CoreSight, SystemVerilog, Verilog, Perl, Python
Responsibilities
Define and document micro-architecture specifications, develop RTL implementations, perform design checks, assess test coverage with verification team, debug design defects
Seniority
Staff, hands-on IC