Senior Verification Engineer, PCIE
Core
Verify the design and implementation of next-generation PCI Express controllers for GPUs and SOCs using UVM and coverage-driven methodologies.
Role type
Senior IC verification engineer (PCIe)
Builds
Verification infrastructure, test plans, and reusable models for PCIe controllers
Domain
Semiconductor / ASIC Design Verification
Deliverable
production ML models
Required skills
ASIC verification, UVM, SystemVerilog, Verilog, constrained random verification, functional coverage, PCIe protocol, IP/sub-system verification
Preferred skills
PCIe Gen3+, CXL architecture, Python, Perl, debugging, analytical skills
Technologies
UVM, VMM, Verilog, SystemVerilog, Python, Perl
Responsibilities
Define verification scope and test plans, build bus functional models/monitors/checkers/scoreboards, verify design correctness at IP/sub-system levels, collaborate with architects and designers
Seniority
Senior, hands-on IC
