Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Core
Physical design of CPU on-chip interconnect networks and last-level caches, focusing on synthesis, timing closure, and achieving area/performance/power goals.
Role type
Senior IC ASIC physical design engineer (cache coherent interconnects)
Builds
Next-generation Nvidia coherent interconnects and system-level caches
Domain
Semiconductor / High-performance computing / AI infrastructure
Deliverable
production ML models | product features
Required skills
Synthesis, timing analysis, floor-planning, high-frequency design, industry standard physical design tools, Verilog, RTL design, DFT, ECO
Preferred skills
Interconnect/cache/core design experience, deep understanding of ASIC design flow
Technologies
Verilog, industry standard physical design tools
Responsibilities
Achieve timing, area, performance, and power goals for on-chip interconnects and caches; collaborate with logic design teams on micro-architecture definition and feasibility; evaluate physical design for next-generation coherent interconnects.
Seniority
Senior, hands-on IC
