Senior DFT Power Methodology Engineer
Core
Innovating DFT Power, Thermal & Voltage Noise Methodology for manufacturing tests on complex semiconductor chips, specifically datacenter GPUs.
Role type
Senior IC DFT Power Methodology Engineer
Builds
Low power & thermal solutions for manufacturing tests and next-gen product DFT methodologies
Domain
Semiconductor / VLSI / Datacenter GPU
Deliverable
production ML models
Required skills
DFT design, Power Analysis, Thermal Analysis, IR Drop analysis, Statistical data analysis, Silicon debug, ATE/SLT platforms, VLSI power/timing/voltage noise
Preferred skills
AI for EDA problem-solving, RTL/clocks design, STA, place-n-route, Post-silicon debug for thermal & IR Drop
Technologies
Applied ML, Gen AI, AI Coding harnesses
Responsibilities
Develop and deploy DFT methodologies using Applied ML & Gen AI; Work on post-silicon data analysis for power to architect next-gen solutions; Mentor junior engineers on test designs and trade-offs
Seniority
Senior, hands-on IC
