Senior Photonic Layout Design Engineer
Core
Physical design and verification of high-speed mixed-signal and Silicon Photonic Integrated Circuits (PICs) from proof-of-concept to manufacturing readiness.
Role type
Senior IC layout design engineer (silicon photonics)
Builds
Silicon Photonics (SiPh) and SERDES products
Domain
Semiconductor manufacturing / Silicon Photonics
Deliverable
production ML models | product features
Required skills
Advanced node semiconductor fabrication knowledge, full-chip layout design, analog circuit layout, Silicon Photonic constraints, device physics, Cadence Virtuoso (Custom Layout, SDL), industry-standard verification suites (Calibre, Hercules, ICV, Dracula, Primeyield), programming/scripting (Python, SKILL, Perl, TCL, C++)
Preferred skills
AI-assisted design methods, layout automation, Design of Experiments (DOEs) optimization
Technologies
Cadence Virtuoso, Calibre, Hercules, ICV, Dracula, Primeyield, Python, SKILL, Perl, TCL, C++
Responsibilities
Lead full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions; execute post-layout verification (DRC, LVS, fill, density); develop complex test structures and certification vehicles; implement AI-assisted design methods and automation scripts to improve productivity and reduce cycle times.
Seniority
Senior, hands-on IC
