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Senior ASIC Design Engineer

US, CA, Santa Clara💼 Full-time💰 $136,000–$136,000🗓 2026-09-14 → 2026-09-25

Core

Design and implement high-performance, area- and power-efficient RTL for world-leading SoCs and GPUs.

Role type

Senior IC ASIC Design Engineer

Builds

SoCs and GPUs for consumer graphics, self-driving cars, and AI

Domain

Semiconductor / VLSI / Computer Architecture

Deliverable

production ML models | product features

Required skills

RTL design and synthesis, logic and timing verification, formal verification, VLSI and Computer Architecture expertise, HDL (Verilog/System Verilog), Perl/Python/C++, logic synthesis and timing analysis, test bench environments (unit/system-level), random stimulus, functional coverage, assertion-based verification

Preferred skills

high-speed energy-efficient data paths knowledge

Technologies

VCS, Debussy, GDB

Responsibilities

Craft architecture and micro-architecture, conduct RTL design and synthesis, perform logic and timing verification, participate in verification builds, collaborate with ASIC development teams

Seniority

Senior, hands-on IC

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