Senior Mixed Signal Design Engineer
Core
Design high-speed I/O SerDes components (PLL, CTLE, ADC, optics) and adaptation algorithms for NVIDIA's AI, gaming, and autonomous driving SoCs.
Role type
Senior Mixed-Signal Design Engineer (High-Speed I/O)
Builds
High-speed SerDes IP blocks and system architectures for complex SoCs
Domain
Semiconductor / High-Speed Digital & Analog Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, high-speed SerDes/PLL analog circuit design, custom digital circuit design, adaptation algorithms (DFE, CTLE, CDR, offset cancellation), Perl/Python scripting
Preferred skills
FPGA emulation, SATA/PCIE/USB protocol knowledge
Technologies
SystemVerilog, Perl, Python, FPGA
Responsibilities
Create accurate SystemVerilog models for analog components; define and verify system architecture specifications with architects and digital designers; streamline workflows with scripts; build scripts for silicon bringup, debug, QA, characterization, and ATE
Seniority
Senior, hands-on IC