Senior Mixed Signal Design Engineer
Core
Designing high-speed memory I/O interfaces (LPDDR, DDR, GDDR, HBM) and SerDes circuits in deep submicron CMOS FinFET processes.
Role type
Senior IC mixed-signal/analog circuit design engineer
Builds
High-speed memory interface chips and SerDes components
Domain
Semiconductor / High-speed digital memory and I/O
Required skills
High-speed memory interface design (LPDDR, DDR, GDDR, HBM), SerDes design, deep submicron CMOS FinFET process knowledge, system-level timing budgeting and analysis, ESD and Latch-Up mitigation, Cadence custom design tools, circuit simulation (Hspice, XA, FineSim, Spectre), layout development, package substrate and board design, power delivery design
Preferred skills
Verilog, Nanotime, Matlab, Lab test and measurement equipment
Technologies
Cadence, Hspice, XA, FineSim, Spectre, LPDDR, DDR, GDDR, HBM, FinFET
Responsibilities
Develop mixed-signal/analog circuits for high-speed memory I/O interfaces, solve circuit development challenges in deep submicron CMOS FinFET processes, take designs through productization, optimize designs with multi-functional teams, lead layout development and ensure compliance with ESD/Latch-Up and reliability rules
Seniority
Senior, hands-on IC
