Senior Mixed Signal Design Engineer
Core
Designing mixed-signal/analog/IO circuits for high-speed memory I/O interfaces in deep submicron CMOS FinFET processes.
Role type
Senior IC analog/mixed-signal design engineer (memory interface)
Builds
High-speed memory interface circuits (LPDDR, DDR, GDDR, HBM) and SerDes
Domain
Semiconductor / High-speed memory / Analog circuit design
Deliverable
production ML models | product features
Required skills
High-speed memory design (LPDDR, DDR, GDDR, HBM), SerDes design, deep submicron CMOS FinFET process knowledge, system-level timing budgeting and analysis, ESD and Latch-Up mitigation, Cadence custom design tools, circuit simulation (Hspice, XA, FineSim, Spectre), layout development
Preferred skills
Package substrate and board design, power delivery network design, Verilog, Nanotime, Matlab, lab test and measurement equipment
Technologies
Cadence, Hspice, XA, FineSim, Spectre, Verilog, Nanotime, Matlab
Responsibilities
Develop mixed-signal/analog circuits for high-speed memory I/O interfaces, solve circuit development challenges in deep submicron CMOS FinFET processes, take designs through productization, optimize designs with multi-functional teams
Seniority
Senior, hands-on IC