Principal Verification Chip Design Engineer
Core
Define and build best-in-class verification methodologies, shared code, and infrastructure to ensure high-quality chip design deliveries at scale.
Role type
Principal verification methodology lead (technical lead)
Builds
Foundational verification flows, shared verification code, and automation infrastructure
Domain
Semiconductor chip design / Verification engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Pre-silicon verification, verification scope definition, risk identification, infrastructure development, design automation partnership, EDA tool integration, verification strategy, training delivery
Preferred skills
Process leadership across multiple groups, simulation performance optimization
Technologies
EDA tools, simulation tools
Responsibilities
Define groundbreaking verification methodologies, mentor designers and verification specialists, lead infrastructure development for design correctness, guide shared verification code development, partner with design automation teams, collaborate with EDA vendors, lead verification strategies and training sessions
Seniority
Principal, technical lead & mentorship
